1. Field of the Invention
The present invention relates to a technique for terminating dangling bonds occurring in a trench-type element isolation region of a semiconductor device or image sensor.
2. Description of the Related Art
Solid-state image sensors, in which pixels including photoelectric conversion elements are arrayed in one or two dimensions, are mounted in electronic devices such as digital cameras, digital video cameras, copiers, and facsimile machines. Types of solid-state image sensors include, for example, CCD image sensors and CMOS-type image sensors.
Recently, with an increase in the number of pixels in solid-state image sensors, miniaturization of the pixels has proceeded apace and the light receiving area of the light receiving elements and the area of the active regions of the transistors that constitute a circuit continue to decrease. In CMOS-type image sensors in particular, because an element isolation region for isolating the light receiving element from the transistor and for isolating the transistors from each other is provided, the area of the element isolation region must be reduced to achieve miniaturization. As the signal load decreases with the miniaturization of the pixels, it becomes necessary to reduce also the dark current of the light receiving area that becomes a noise component.
To cope with such miniaturization, Shallow Trench Isolation (STI) has come to be employed, which involves filling the inside of a trench in the semiconductor substrate with insulating film as the element isolating region.
It is known that, compared to use of a selective oxide layer fabricated using the Local Oxidation of Silicon (LOCOS) method, use of an STI structure as the element isolation region in a semiconductor device causes more crystal defects adjacent to the element isolation region and, as a result, an increase in leakage current. It is known that the cause of this leakage current is high interface trap density resulting from many deformations and crystal defects remaining in the interface between the silicon and the silicon oxide film at the inner walls of the STI.
In Japanese Patent Laid-Open No. 08-316465, a method of implanting fluorine atoms in the interface between the silicon oxide layer and the silicon substrate and terminating dangling bonds with the fluorine to produce Si—F bonding thereby reducing the crystal defects is disclosed.
In addition, implanting fluorine ions before and after formation of the gate insulating film is known to adversely affect the device formation regions due to implantation damage and to invite a reduction in the reliability of the gate electrode and gate insulating film due to the mixing in of a large amount of fluorine (Japanese Patent Laid-Open No. 2004-356554, Japanese Patent Laid-Open No. 2001-156291).
However, when the interface trap reduction technique described in Japanese Patent Laid-Open No. 08-316465 is applied to solid-state image sensors, a problem arises in that photoelectric conversion element dark current (or leakage current) and dark current (or leakage current) in the trench-type element isolation region are not sufficiently reduced. With digital camera solid-state image sensors, it is necessary to keep the dark current on the order of femto amperes (fA) per pixel, which is a size that is far smaller than that allowed for CPU and other logic circuits or for memory devices. Thus, it is clear that the conventional technique must be improved in order to be used with solid-state image sensors.
In addition, as described in Japanese Patent Laid-Open No. 2004-356554 and Japanese Patent Laid-Open No. 2001-156291, implanting fluorine ions before and after formation of the gate insulating film is known to pose a risk of damaging the device formation regions. The active region of a solid-state image sensor has photoelectric conversion elements as well as MOS transistors, and for this reason damage to the gate oxide film must be kept to a minimum. Moreover, although the reliability of the oxide film is not a major problem in the element isolation region, due to miniaturization of the pixels it is necessary to keep crystal defects and interface traps in the element isolation region nearest the photoelectric conversion elements to a minimum.